1. Field of the Invention
The present invention generally relates to a data processing apparatus and, more particularly, to a data processing apparatus having a data memory device which can be efficiently accessed by a processor.
2. Description of the Related Art
A data processing apparatus generally comprises a processor, a program RAM which stores programs and a data RAM which stores data to be processed. The processor reads the data in the data RAM in accordance with the programs stored in the program RAM so as to process or calculate the read data. The processed data is restored in the data RAM or stored in an external memory device.
In a geometry processing unit specific to a geometrical image processing application such as polygon processing, a digital signal processor (DSP) is used as a processor so as to perform specific calculations or operations at high speed. A description will be given below of a specific content of the process performed by such a unit.
1) Data to be supplied to a DSP is arranged in an order of use by the DSP. Thus, the DSP can perform calculations based on the data sequentially supplied thereto. That is, the DSP can perform a set of calculations by setting the address corresponding to the first data and the addresses for the rest of the data can be set by using an automatic incrementing function of the address.
2) When a different calculation is performed based on the result of a calculation, the result (resultant data) of the calculation is not arranged in the order of use by the DSP. That is, the order of addresses in which the resultant data is stored does not match the order of use by the DSP. Thus, the automatic incrementing function is not applicable to set the addresses for the resultant data. In the conventional data processing apparatus, the addresses must be reset every time the resultant data is used.
FIG. 1 is an illustration of an operation of the DSP mentioned above. For example, the data "A, B, C, D, E, F" are arranged in the order of use by the DSP. The result of calculation based on the data "A, B, C, D, E, F" is now assumed to be "a, b, c, d, e". Additionally, the order of use of the data "a, b, c, d, e" assumes that the data "a" is used fifth, the data "b" is used second, the data "c" is used first, the data "d" is used third, and the data "e" is used fourth. In such a case, the DSP sets the address of the resultant data "c" first to use the data "c", then, the DSP sets the address of the resultant data "b" to use the data "b", and so on.
A description will now be given of contents of another operation performed by the DSP.
3) The DSP performs calculations based on externally input data. The result of calculation is transferred to an external device, and simultaneously written in the internal data RAM.
4) In this case, the conventional data processing apparatus separately performs an operation for writing the resultant data in the internal data RAM and an operation for writing the resultant data in an output register to transfer the resultant data to the external device. Further calculations may be performed based on the resultant data stored in the internal data RAM, or calculations may be performed based on the data which was processed in the external device and returned to the data processing apparatus.
FIG. 2 is an illustration for explaining the operation described in the above items 3) and 4). For example, it is assumed that the result of calculation "C" is obtained by using the data "A, B". The result of calculation "C" is written in both the internal data RAM and the output register by separate operations. An additional calculation is performed by using the result of calculation "C". Additionally, the result of calculation "C" is processed by the external device, and the data processing apparatus performs a calculation using the result of the operation performed by the external device.
As mentioned above, in the conventional data processing apparatus, the address is set every time the results of a calculation is used, as appreciated from the operation described in the above-mentioned item 2). Thus, the number of steps performed by the DSP is large, and this prevents increase of the calculation speed of the DSP. Additionally, as appreciated from the operation of the above-mentioned item 4), since the results of a calculation is written in both the internal data RAM and the output register by separate operations, substantially the same writing operation is performed twice. This also increases the number of steps performed by the DSP, and there is a problem in that it is difficult to perform a high speed calculation.
The data processing apparatus disclosed in Japanese Laid-Open Patent Application No. 4-273366 is provided with two data RAMs which are switchable by a register. In this data processing apparatus, after data is read from one of the data RAMs and a calculation is performed on the read data and the result is stored in one of the data RAMs, the operation is switched to perform a similar operation with respect to the other one of the data RAMs. While the operation is performed with respect to the other one of the data RAMs, an external device or circuit can perform first the data stored in the first one of the data RAMS. Thus, a time spent on the input and output operation of the data stored in the data RAMs can be saved. However, this method is effective when the data in the data RAMs is sequentially read from the upper address. That is, the data stored in the data RAMs is not sequentially arranged, and the operation the above-mentioned item 2 is still required.
Additionally, if the data RAMs to be used can be switched as taught in the Japanese Laid-Open Patent Application No. 4-273366, the data to be used internally and externally can be written in one of the data RAMs so that the data stored in one of the data RAMs is read alternatively by the internal processor and the external device or circuit. This eliminates the duplicate writing operation for the data to be used by the internal processor and the external device. However, if the data RAMs are alternatively used, the switching of the data RAMs cannot be performed until the set of operations of the internal processor or the external device has been completed. This causes a new problem in that the interim result of a calculation cannot be used even when it is required. Thus, in this case, the result of a calculation must be written in each of the data RAM and the output register.